This invention is related to the field of charge pumps, and particularly their use in phase locked loops (PLLs).
Charge pumps are employed in a wide variety of circuits, such as voltage doublers, clock doublers, phase-locked loops (PLLs), delay locked loops, memory systems, etc. Generally, a charge pump is configured to provide or remove charge from an output node of the charge pump in response to input up and down signals (respectively).
Charge pumps may experience error during operation from a variety of sources. Charge injection error may occur during switching of the transistors internal to the charge pump in response to the up and down signals. Clock feedthrough error may also be experienced across the parasitic gate to source and drain capacitances. Furthermore, transistor imperfections such as body effect, channel length modulation, drain induced barrier loading (DIBL), etc. may cause errors in the charge pump""s operation.
These errors affect the amount of charge provided on or removed from the output node of the charge pump in response to a particular pulse width of the up and down signals, respectively. At reduced operating voltages (which are become more and more common as integrated circuit fabrication technologies advance), these errors are magnified.
A charge pump includes at least one switching transistor for switching current on or off in response to an up or down signal, a pair of transistors (one coupled to the source and the other to the drain of the switching transistor) each having its source and drain shorted and coupled to receive a complement of the signal on the gate terminal of the switching transistor on their gate terminals, and a fourth transistor coupled to the drain of the switching transistor and a power supply. The pair of transistors may reduce charge injection error by the switching transistor. They are activated concurrent with the deactivation of the switching transistor, and thus their channels are acquiring charge at a time when the charge injection may occur from the switching transistor. The acquired charge may include the injected charge. Additionally, since the gate terminals of the pair of transistors are transitioned in the opposite direction as the gate terminal of the switching transistor, clock feedthrough from the pair of transistors may reduce clock feedthrough error from the switching transistor. In one implementation, the pair of transistors may be sized approximately xc2xd the size of the switching transistor. Thus, parasitic capacitances between the gate terminal of the pair and the source and drain may be approximately xc2xd of the parasitic capacitances of the switching transistor. However, since the source and drain of each of the pair of transistors is shorted, the parasitic capacitances in parallel add to produce approximately the same parasitic capacitance on the source or drain as the switching transistor has. The fourth transistor may provide for active shutoff of a current transistor being switched by the switching transistor, by actively charging the source of the current transistor to a voltage which is not exceeded by the gate terminal of the current transistor.
In one embodiment, the charge pump may employ dummy loads to more accurately balance the load on the up and down signals received by the charge pump, in order to more evenly balance the up and down currents on the output node of the charge pump.
Broadly speaking, a circuit is contemplated. The circuit comprises a first, second, third, and fourth transistor. The first transistor, second transistor, and third transistor are coupled in series. The first transistor includes a first terminal, a second terminal, and a first gate terminal. The second transistor includes a third terminal, a fourth terminal, and a second gate terminal. The third transistor includes a fifth terminal, a sixth terminal, and a third gate terminal. The first terminal, the second terminal, and the third terminal are to connected to a first node. The fourth terminal, the fifth terminal, and the sixth terminal are connected to a second node. The second gate terminal is coupled to receive a first signal, and the first gate terminal and the third gate terminal are coupled to receive a complement of the first signal. The fourth transistor has a seventh terminal, an eighth terminal, and a fourth gate terminal. The seventh terminal is coupled to the first node, the eighth terminal is coupled to a power supply, and the fourth gate terminal is coupled to receive the first signal.
Additionally, a method is contemplated. A first transistor having a first terminal and a second terminal is activated. The first transistor is deactivated. Concurrent with activating the first transistor, a second transistor having a third terminal and a fourth terminal each connected to the first terminal and a third transistor having a fifth terminal and a sixth terminal each connected to the second terminal are deactivated. Concurrent with deactivating the first transistor, the second transistor and the third transistor are activated. Concurrent with deactivating the first transistor, a fourth transistor having a seventh terminal coupled to the first terminal and an eighth terminal coupled to a power supply is activated.